Introduction
As a verification engineer working on RISC-V designs, I’ve learned that lockstep co-simulation is one of the most effective ways to identify failing tests better and debug those failures. By running the RTL alongside a validated reference model and checking architectural state at each instruction retirement, mismatches are reported immediately, which avoids wasted simulation cycles and allows debugging exactly at the point of failure.
Why lockstep co-simulation matters
RISC-V’s flexibility is both a strength and a challenge. Designs can be single or multi-hart, with or without caches, adopting weak or strong memory models. A practical verification strategy must integrate with existing simulation approaches, which for SV/UVM environments means reuse of scoreboards and coverage, and fit naturally into debug flows with tools like Verdi. Using RVVI as the interface standardises the exchange of retire, state, and event information between DUT, testbench, and reference model, which makes integration easier. It also ensures that asynchronous events such as interruptions, exceptions, and debug transitions can be introduced and remain reproducible for analysis [1].
How retirement-level lockstep works
The methodology is simple and effective. The RTL and reference model run the same programme under a co-simulation harness. At each retire event, the architectural state is captured and compared immediately. Any divergence is flagged with the retire index and expected versus actual values. As the comparison is done at retirement rather than using transient pipeline states, debug focuses on architecturally visible behaviour and avoids false positives [2].
Figure 1. Retirement-level lockstep co-simulation flow. The RTL and reference model run the same programme in parallel and are synchronised at instruction retirement. Configurable architectural state is compared at each retire, with immediate mismatch reporting for faster debug [2].
Configurable internal state
The tool provides a configurable state mask, allowing for a structured approach to checking. For example, bring-up often starts with PC-only checks and then expands to PC plus GPRs for control and datapath validation. Adding CSRs exercises the privilege and exception handling. When sign-off confidence is required, selected memory regions or the complete architectural state can be compared. This scalability makes lockstep applicable from early RTL to final verification sign-off [2].
Benefits over traces and self-checks
Unlike trace-based flows or self-checking tests, lockstep comparison flags the first divergent instruction rather than surfacing problems at the end of a test run. This immediate flagging accelerates debugging and uncovers issues such as CSR side effects, privilege transitions, or subtle ordering errors that traces or self-checks may miss. Each failure maps to a specific retire index and instruction, making reruns deterministic and root cause analysis faster [2].
Debug at the point of failure.
On a mismatch, the flow records the retire index, instruction context, expected versus actual values, and a short preceding window. Engineers can jump directly into waveforms or logs, isolate the write-back or exception logic, apply a fix, and confirm resolution by rerunning the same seed. This point-of-failure workflow shortens debug and is well supported by modern toolchains [2].
Stimulus that exposes real bugs
A comprehensive testbench stimulus typically combines constrained-random instruction streams with directed ISA tests, enhanced with asynchronous events injected at random retire points. RVVI extensions ensure these randomised injections remain reproducible for debugging. Stressing virtual memory operations, exploring CSR side effects, and testing weak versus strong memory models reliably trigger corner-case bugs and strengthen overall verification [1].
Integration into existing flows
Lockstep co-simulation drops into existing flows. A UVM component synchronises RTL and reference model at retirement, exchanges state and events via RVVI, and feeds results to scoreboards and coverage. Synopsys documents this methodology for ImperasDV, showing retirement-level compare with immediate mismatch reporting and integration with VCS and Verdi [3]. Wider industry collaborations between Synopsys and Imperas have also highlighted SystemVerilog-based co-simulation flows where reference models plug directly into RTL verification [4].
Performance and practicality
Teams often begin with PC plus GPRs for speed, then widen to CSRs and memory as confidence targets grow. Non-deterministic sources such as timers or random I/O are masked or stubbed to avoid spurious mismatches. An RVVI-based handshake enables randomised interrupts and debug requests while keeping runs deterministic for replay. For long regressions, checkpoints and consistent seed logging ensure repeatability [1].
Conclusion
Retirement-level lockstep co-simulation gives RISC-V teams a rigorous path to architectural correctness. By comparing the configurable state at each retire, divergences are caught immediately, wasted cycles are avoided, and debugging happens at the exact point of failure. With SV/UVM integration, RVVI interfaces, validated reference models such as ImperasFPM, and tool support from VCS and Verdi, this approach scales from bring-up to sign-off and complements trace-based and self-check methods [2].
Next Steps in RISC-V Verification
If you want to strengthen your RISC-V verification flow with proven methodologies, retirement-level lockstep co-simulation can give you the confidence you need. By combining Synopsys VCS and Verdi with ImperasDV and RVVI integration, your team can easily accelerate debug, catch subtle bugs, and scale from bring-up to sign-off.
To learn more about how these flows can be applied to your projects, visit Synopsys for detailed resources and expert guidance on RISC-V processor verification.
Appendix A. Key Definitions
Lockstep Co-Simulation:
- Running RTL (design under test) in parallel with a reference model, synchronised at each instruction retirement, with architectural state compared to detect mismatches.
- Instruction Retirement:
- The point is when an instruction has completed execution and its results are committed to the architectural state.
Architectural State:
- The processor state visible at the ISA level, including program counter (PC), general-purpose registers (GPRs), control and status registers (CSRs), and memory contents relevant to execution.
- RVVI (RISC-V Verification Interface):
- An open standard interface for exchanging retire, state, and event information between the RTL, testbench, and reference models.
Step-and-Compare:
- A methodology where RTL and reference model states are captured and compared at each retire step, providing immediate mismatch reporting.
- Asynchronous Events:
- Interrupts, debug requests, or exceptions are injected at arbitrary retire points to stress the design while keeping runs reproducible for debug.
ImperasFPM Reference Model:
- A fast processor model used as the reference in lockstep comparisons for RISC-V cores.
Appendix B. Synopsys Tools Supporting Lockstep Flows
Synopsys VCS®:
- Industry-standard RTL simulator used to execute the design under test in co-simulation.
- ImperasDV™ (via Synopsys partnership):
- Provides the reference model and lockstep co-simulation methodology, integrating seamlessly with SV/UVM flows and RVVI.
Verdi® Debug Platform:
- A debug environment where mismatches, retire indices, and architectural state differences can be inspected with waveform correlation.
References
[1] S. Davidmann, I. Software, A. Sutton, and L. Moore, “Understanding the RISC-V Verification Ecosystem,” 2023. Accessed: Aug. 30, 2025. [Online]. Available: https://dvcon-proceedings.org/wp-content/uploads/3021-Understanding-the-RISC-V-Verification-Ecosystem.pdf
[2] S. Davidmann, “RISC-V Processor Verification Requires the Full Toolbox,” in Verification Futures, UK: 2025, p. 13.
[3] Synopsys, “ImperasDV – RISC-V Processor Verification Made Easy.” Accessed: Aug. 30, 2025. [Online]. Available: https://www.synopsys.com/verification/imperasdv.html
[4] Design-Reuse News, “Imperas Collaborates with Synopsys on SystemVerilog-based RISC-V Verification,” Design And Reuse, Feb. 27, 2023. Accessed: Aug. 30, 2025. [Online]. Available: https://www.design-reuse.com/news/13687-imperas-collaborates-with-synopsys-on-systemverilog-based-risc-v-verification
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